This invention relates to a data and clock recovery PLL (phase locked loop) circuit which uses a Windowed Phase Comparator to extract a clock signal from its random input data in a data transmission system, or the like.
Phase locked loop circuits are very important components in data transmission systems. They are used in many different applications for example to eliminate skew between communication chips to recover a clock signal from random input data.
A conventional phase locked loop circuit includes a Gilbert Multiplier type phase detector and an emitter-coupled multivibrator VCO (voltage controlled oscillator). The conventional phase locked loop circuit can maintain stable lock for tens of consecutive identical bits without requiring a large external capacitor (to increase the RC time constant of the low-pass filter).
However, the phase locked loop circuit loses the lock when the number of consecutive identical bits reaches the hundreds. In addition, the phase locked loop circuit may fail to lock altogether when the input data frequency differs significantly from the phase locked loop's free-running frequency (or the initial oscillation frequency at time t=0) Moreover, the phase locked loop circuit suffers from harmonic lock.